1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device including a transistor (ESD-Tr) having an Elevated Source Drain (ESD) (it is also referred to as Raised Source Drain (RSD)) structure.
2. Description of the Related Art
In a semiconductor device, transistors having different gate lengths are frequently provided as mixed on a single substrate.
For example, in the semiconductor device such as DRAM (Dynamic Random Access Memory), memory cell transistors that are connected to memory devices such as capacitors, transistors of array circuits (X and Y decoders) for controlling memory cells and transistors for peripheral circuits for controlling the array circuits and input/output of data are formed on a semiconductor substrate. Generally, transistors finer (having a shorter gate length) than the transistors of the array circuit and the peripheral circuit are formed in a memory cell region, from a standpoint of providing cells in a predetermined area of the memory cell region as much as possible.
Conventionally, the transistors of the array circuit and the peripheral circuit (hereinafter, the transistors of the array circuit and the peripheral circuit are commonly referred to as “peripheral circuit transistors”), for which a high speed operation is required, are generally formed with high concentration diffusion layers to reduce resistance of source/drain. When the high concentration diffusion layer is formed, a short-channel effect which results from diffusion of impurities to a channel becomes actually evident. In order to prevent the short-channel effect, it has been suggested to provide a LDD (Lightly Doped Drain) structure or extension area. Furthermore, as a generation of semiconductor device development is advanced, it is required to form the source/drain shallower from a surface of the substrate than ever before.
Accordingly, a structure has been suggested in which epitaxially grown silicon layers are formed on the source/drain and the source/drain area is elevated beyond the original substrate surface, thereby becoming a junction depth from the substrate surface shallower, while securing a substantial junction depth of the source/drain area. Such a structure is referred to as an ESD structure.
In order to form an ESD structure, the following method is generally used. A gate electrode is first formed on a substrate and a shallow diffusion layer (low concentration diffusion layer) is formed by using the gate electrode as a mask. Continuously, sidewall insulating films are formed on sidewalls of the gate electrode, an epitaxially grown silicon layer is formed on an exposed surface of the substrate, and impurity ion implantation for forming a high concentration diffusion layer is performed to form high concentration diffusion layers in the epitaxially grown silicon layer and the substrate surface.
At this time, it is known that when a silicon oxide film is formed as the sidewall insulating film, the growth of the epitaxially grown silicon layer is impeded at a contact surface with the silicon oxide film and a facet is thus formed (refer to JP-A No. 2000-49348). When the ion implantation for forming a high concentration diffusion layer is performed through the epitaxially grown silicon layer with such a facet, the diffusion layer below the facet is deeper (refer to FIG. 10 in JP-A No. 2000-49348), so that problems in extended short-channel effect or increase of parasitic capacity in the diffusion layer are caused. In addition, it is disclosed in JP-A No. 2000-49348 ([0055] and [0056] paragraphs) that when a thickness of the epitaxially grown silicon layer is under about 100 nm, the facet is not generated on a sidewall insulating film made of insulating material containing nitrogen, such as silicon nitride, silicon oxynitride and the like.
Meanwhile, in order to form the cell transistors finer and in higher dense than the peripheral circuit transistors from a standpoint of increasing the memory capacity, a gate length is further reduced and a gate interval is also narrowed. Accordingly, a shallower junction is required so as to suppress the short-channel effect. Additionally, in the cell transistors that are formed to be finer and in higher dense, it is more difficult to form a contact that is connected to the diffusion layer and a process of forming a self-aligned contact (SAC method) is mainly used.
As the cell size is reduced, contact size and junction depth tend to decrease. Thereby, it is difficult to secure electric properties of the transistor, particularly contact resistance. In order to solve the problems, JP-A No. 2003-338542 discloses a landing plug structure in which an epitaxially grown single-crystal silicon layer is formed on a surface of a semiconductor substrate and polysilicon is formed thereon. The epitaxially grown single-crystal silicon layer is also referred to as a landing pad. By forming the landing pad, the increase in contact resistance due to the natural oxidation film on the substrate surface is suppressed.
In the meantime, from a standpoint of process simplification, it is generally performed to make processes of manufacturing the cell transistor and the peripheral circuit transistor common. When forming the transistor having the ESD structure and the cell contact by the SAC method, a sidewall film is commonly formed on the gate sidewall. In addition, when the landing plug structure is applied to the memory cell region, a selective epitaxial growth is commonly performed on the substrate surface. However, as the memory cell size is reduced, it is required to reduce a width of the sidewall or a thickness of the single crystal silicon layer by the selective epitaxial growth. Additionally, in the peripheral circuit transistor, it is difficult to suppress the short-channel effect by the ESD structure if requirements for the cell transistor are met.
If the cell transistor and the peripheral circuit transistor are separately produced, it is possible to produce transistors that satisfy characteristics required for each transistor. However, the number of processes is increased and the cost is also increased.
Conventionally, in a transistor to which the ESD structure is not applied, as a method of making the sidewall width of the peripheral circuit transistor thicker than the sidewall width of the cell transistor, it has been adopted a method in which a two-layered film of a silicon nitride film and a silicon oxide film is used as a sidewall film and the silicon oxide film is selectively etched from a memory cell region. However, since the lower silicon nitride film has a thickness that is suitable for a sidewall of the cell transistor and the selectively epitaxially grown silicon layer is typically formed to be thicker than its thickness, the lower silicon nitride film is grown to a thickness contacting the upper silicon oxide film. As a result, in the ESD structure, a shape involving a facet due to the selective epitaxial growth having selectivity for the silicon oxide film is regenerated, as described above.